View XR-215ACP_1338240.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

XR-215A
VCC 16
VEE 9
COMP
7 1
OPAMP
Op Amp
8
OPAMPO
PHCP1
4 Phase 6 Comparator
3
PCO2
PHCP2
2
PCO1
BIAS
5
VSI VGC RGS
12 11 10 VCO 15 VCOO
TCI1
13
TCI2
14
Figure 1. XR-215A Block Diagram
Rev. 1.01 2
XR-215A
PIN CONFIGURATION
OPAMP PCO1 PCO2 PHCP1 BIAS PHCP2 COMP OPAMPO
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
VCC VCOO TCI2 TCI1 VSI VGC RGS VEE
OPAMP PCO1 PCO2 PHCP1 BIAS PHCP2 COMP OPAMPO
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC VCOO TCI2 TCI1 VSI VGC RGS VEE
16 Lead 300 Mil PDIP
16 Lead SOIC (Jedec, 0.300")
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol OPAMP PCO1 PCO2 PHCP1 BIAS PHCP2 COMP OPAMPO VEE RGS VGC VSI TCI1 TCI2 VCOO VCC Type I O O I I I I O I I I I I O Description Operational Amplifier Input. Phase Comparator Output 1. Phase Comparator Output 2. Phase Comparator Input 1. Phase Comparator Bias Input. Phase Comparator Input 2. Operational Amplifier Frequency Compensation Input. Operational Amplifier Output. Negative Power Supply. Range Select Input. VCO Gain Control. VCO Sweep Voltage Input. Timing Capacitor Input. The timing capacitor connects between this pin and pin 14. Timing Capacitor Input. The timing capacitor connects between this pin and pin 13. VCO Output. Positive Power Supply.
Rev. 1.01 3
XR-215A
DC ELECTRICAL CHARACTERISTICS
Test Conditions: VCC= 12V (single supply), TA = 25C, Test Circuit of Figure 3 with C0 = 100 pF, (silver-mica) S1,S2, S5, closed, S3, S4 open unless otherwise specified.
Parameter GENERAL CHARACTERISTICS Supply Voltage Single Supply Split Supply Supply Current Upper Frequency Limit Lowest Practical Operating Frequency VCO Section Stability: Temperature Power Supply Sweep Range Output Voltage Swing Rise Time Fall Time Phase Comparator Section Conversion Gain Output Impedance Output Offset Voltage OP AMP Section Open Loop Voltage Gain Slew Rate Input Impedance Output Impedance Output Swing Input Offset Voltage Input Bias Current Common Mode Rejection 7 0.5 66 80 2.5 2 2 10 1 80 90 10 dB V/msec MW kW Vp-p mV nA dB RL = 30kW From Pin 8 to Ground S2 Open AV = 1 2 6 20 100 V/rad kW mV VIN > 50mV rms (See Characteristic Curves) Measured Looking into Pins 2 or 3 Measured Across Pins 2 and 3 VIN = 0, S5 Open 5:1 1.5 250 0.1 8:1 2.5 20 30 Vp-p ns ns 10pF to Ground at Pin 15 600 ppm/C %/V See Figure 7, 0C TT < 70C VCC > 10V S3 Closed, S4 Open, 0 < VS < 6V See Figure 10, C0 = 2000pF S5 Open 5 +2.5 8 20 11 25 0.5 26 +13 15 V V mA MHz Hz Min. Typ. Max. Unit. Conditions
Figure 3 Figure 4 Figure 3 Figure 3, S1 Open, S4 Closed
C0 = 500mF (Non-Polarized)
Note: Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 1.01 4
XR-215A
DC ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter SPECIAL APPLICATIONS A) FM Demodulation Test Conditions: Test circuit of Figure 5, VCC = 12V, input signal = 10.7MHz FM with Df = 75kHz. fmod = 1kHz. Detection Threshold Demodulated Output Amplitude Distortion (THD) AM Rejection Output Signal/Noise 0.8 500 0.15 40 65 0.5 3 mV rms mV rms % dB dB VIN = 10mV rms, 30% AM 50W source Measured at Pin 8 Min. Typ. Max. Unit Conditions
B) Tracking Filter Test Conditions: Test circuit of Figure 6, VCC = 12V, fo = 1 MHz, VIN = 100mV rms, 50W source. Tracking Range (% of fo) Discriminator Output DVOUT Df / fo 50 mV/% Adjustable - See Applications Information +50 See Figure 5 and Figure 25
Note: Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 volts Power Dissipation (Package Limitation) Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . 625mW Derate above 25C . . . . . . . . . . . . . . . . . . . . 5mW/C SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Derate above 25C . . . . . . . . . . . . . . . . . . . . 4mW/C Temperature Storage . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C
Rev. 1.01 5
XR-215A
16
3
2
1
8 7 14 13 6 5 4 11 12 10 9 15
Figure 2. Equivalent Schematic Diagram
SYSTEM DESCRIPTION The XR-215A monolithic PLL system consists of a balanced phase comparator, a highly stable voltagecontrolled oscillator (VCO) and a high speed operational amplifier. The phase comparator outputs are internally connected to the VCO inputs and to the noninverting input of the operational amplifier. A self-contained PLL System is formed by simply AC coupling the VCO output to either of the phase comparator inputs and adding a low-pass filter to the phase comparator output terminals. The VCO section has frequency sweep, on-off keying, sync, and digital programming capabilities. Its frequency is highly stable and is determined by a single external capacitor. The operational amplifier can be used for audio preamplification in FM detector applications or as a high speed sense amplifier (or comparator) in FSK demodulation. DESCRIPTION OF CIRCUIT CONTROLS Phase Comparator Inputs (Pins 4 and 6) One input to the phase comparator is used as the signal input. The remaining input should be AC coupled to the
Rev. 1.01 6
VCO output (pin 15) to complete the PLL (see Figure 3). For split supply operation, these inputs are biased from ground as shown in Figure 4. For single supply operation, a resistive bias string similar to that shown in Figure 3 should be used to set the bias level at approximately VCC/2. The DC bias current at these terminals is nominally 8mA. Phase Comparator Bias (Pin 5) This terminal should be DC biased as shown in Figure 3 and Figure 4, and AC grounded with a bypass capacitor. Phase Comparator Outputs (Pins 2 and 3) The low frequency (or DC) voltage across these pins corresponds to the phase difference between the two signals at the phase comparator inputs (pins 4 and 6). The phase comparator outputs are internally connected to the VCO control terminals (see Figure 2.) One of the outputs (pin 3) is internally connected to the noninverting input of the operational amplifier. The low-pass filter is achieved by connecting an RC network to the phase comparator outputs as shown in Figure 15.
XR-215A
5K
+12V 5K 0.1mF
0.1mF 2K U1 5 0.1mF Signal Input 1K Sweep Input Vs S3 S4 5K 6 11 12 10 VEE 9 13 5pF S1 RF 100K 14 2 VCO
Op Amp
2K
Phase Comp.
16 VCC
4 S5
XR-215A 0.1mF 15 8 7 300pF S2 10K Demodulated 0.068mF Output 10K VCO Output
750
31
100pF 2nF
RP 10K 2nF
50
50
Figure 3. Test Circuit for Single Supply Operation
Rev. 1.01 7
XR-215A
+6V
0.1mF 0.1mF 2K U1 5 0.1mF Signal Input 50W 2K 5K 6 Phase Comp. XR-215A 15
Op Amp
16
VCC 4 2K 0.1mF
11 12 VCO
S4 VEE
VCO Output 10K
10 9 13 14 100pF 2 31
8 7 300pF
750
-6V 10K 0.068mF RF 100K
Demodulated Output
-6V RP 10K 2nF 2nF
50
50
Figure 4. Test Circuit for Split-Supply Operation
Rev. 1.01 8
XR-215A
+12V
0.1mF 0.1mF 2K U1 5 FM Input (50W Source) 0.1mF 3K 6 Phase Comp. 16 VCC 4 XR-215A 15
VCO
Op Amp
2K
1K 0.1mF
11 12 10 VEE 9 13 14 2
VCO Output 10K
8 7 300pF 7.5K 10nF
31
750 30pF
Demodulated Output
RP 10K 1nF 1nF
RF 100K
50
50
Figure 5. Test Circuit for FM Demodulation
Rev. 1.01 9
XR-215A
+12V 5K 5K 0.1mF 0.1mF 2K U1 5 0.1mF Signal Input 50W 6 Phase Comp. 16 VCC 4 XR-215A 0.1mF 12 10 VEE 9 13 C0 VCO
Op Amp
2K
R0 2K
11
15 8 7 300pF 1K 10K
VCO Output
14 200pF
2
31
Demodulated Output
RP 20K 5nF 5nF
RF 40K
50
50
Figure 6. Test Circuit For Tracking Filter
Rev. 1.01 10
-800
IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII
10KHz 100KHz 1MHz VCC = 12V R0 = 5kW
Figure 7. Typical VCO Temperature Coefficient Range as a Function of Operating Frequency (Pin 10 open)
VCO Temperature Coefficient (PPM/ C)
-400
800
400
107
IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII
10 102 Pin 10 Open 103 VCO Frequency (Hz) Rx=750W Between Pins 9 & 10 104 105 106 107
Rev. 1.01
Figure 8. VCO Free Running Frequency vs. Timing Capacitor
102
Timing Capacitance C 0 (pF)
103
104
105
106
0
VCO Frequency (Hz)
11
10MHz
XR-215A
XR-215A
VCO Timing Capacitor (Pins 13 and 14) The VCO free-running frequency, fo, is inversely proportional to timing capacitor C0 connected between pins 13 and 14. (See Figure 8.) VCO Output (Pin 15) The VCO produces approximately a 2.5Vp-p output signal at this pin. The DC output level is approximately 2 volts below VCC. This pin should be connected to pin 9 through a 10kW resistor to increase the output current drive capability. For high voltage operation (VCC > 20V), a 20kW resistor is recommended. It is also advisable to connect a 500W resistor in series with this output for short circuit protection.
1.0
0.1
0.01
0.1
Figure 9. Phase Comparator Conversion Gain, Kd, versus Input Amplitude
Rev. 1.01 12
IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII
2V/RAD High Level Input Constant = 1V rms 1 10 100 1000 Low Level Input Input Amplitude (mV rms)
Phase Comparator Conversion Gain K d
IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII
Vs 0 Rs 2K 2K 16 14 12 11 -2 9 VCC
VCO
Note: VSO VCC - 5V = Open Circuit Voltage at pin 12
Rev. 1.01
1
Normalized Frequency (f/fo)
2
3
4
5
+2
Figure 10. Typical Frequency Sweep Characteristics as a Function of Applied Sweep Voltage
Net Applied Sweep Voltage VS - VSO (Volts)
10
Co
13 15
Rx
-4
13
Fo OUTPUT -6 Bias Pins 1,4,5,6 to VCC/2 -8 -10 RX=750W RX=1
XR-215A
-12
XR-215A
100
80
60
40
20
-20
100H
VCO Sweep Input (Pin 12) The VCO Frequency can be swept over a broad range by applying an analog sweep voltage, VS, to pin 12 (see Figure 10.) The impedance looking into the sweep input is approximately 50W. Therefore, for sweep applications, a current limiting resistor, RS, should be connected in series with this terminal. Typical sweep characteristics of the circuit are shown in Figure 10. The VCO temperature dependence is minimum when the sweep input is not used. CAUTION: For safe operation of the circuit, the maximum current, IS, drawn from the sweep terminal should be limited to 5mA or less under all operating conditions. ON-OFF KEYING: With pin 10 open circuited, the VCO can be keyed off by applying a positive voltage pulse to the sweep input terminal. With RS = 2kW, oscillations will stop if the applied potential at pin 12 is raised 3 volts above its open-circuit value. When sweep, sync, or on-off keying functions are not used, RS is not necessary.
Rev. 1.01 14
IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII
RF Rs 1
Open Loop Response
0.1mF
1K
8
AV = 1000 RF = 1M
3
Vout
Vin
Cc
Voltage Gain (dB)
AV = 100 RF = 100K
AV = 10 CC = 50pF; RF = 10K
0
AV = 1 CC = 300pF; RF = 1K
1KHz
10KHz
100KHz
1MHz
10MHz
Frequency
Figure 11. XR-215A Op Amp Frequency Response
XR-215A
Internal Bias T1 1.3V
I1
I2 10
Range Select > 3V, F1
T2
Input 600 RX 0V, Fo Fo = F1(1+(0.6/RX))
Figure 12. Explanation of VCO Range-Select Controls
Range-Select (Pin 10) The frequency range of the XR-215A can be extended by connecting an external resistor, RX, between pins 9 and 10. With reference to Figure 12, the operation of the range-select terminal can be explained as follows: The VCO frequency is proportional to the sum of currents I1 and I2 through transistors T1 and T2 on the monolithic chip. These transistors are biased from a fixed internal reference. The current I1 is set internally, whereas I2 is set by the external resistor RX. Thus, at any C0 setting, the VCO frequency can be expressed as: The range select terminal can also be used for fine tuning the VCO frequency, by varying the value of RX. Similarly, the VCO frequency can be changed in discrete steps by switching in different values of RX between pins 9 and 10. Digital Programming Using the range select control, the VCO frequency can be stepped in a binary manner, by applying a logic signal to pin 10, as shown in Figure 12. For high level logic inputs, transistor T2 is turned off, and RX is effectively switched out of the circuit. Using the digital programming capability, the XR-215A can be time-multiplexed between two separate input frequencies, as shown in Figure 19 and Figure 20. Amplifier Input (Pin 1) This pin provides the inverting input for the operational amplifier section. Normally it is connected to pin 2 through a 10 kW external resistor (see Figure 3 or Figure 4.)
f0 + f1
1 ) 0.6 RX
where f1 is the frequency with pin 10 open circuited and RX is in kW. External resistor RX (750W) is recommended for operation at frequencies in excess of 5MHz.
Rev. 1.01 15
A
9
XR-215A
Amplifier Output (Pin 8) This pin is used as the output terminal for FM or FSK demodulation. The amplifier gain is determined by the external feedback resistor, RF, connected between pins 1 and 8. Frequency response characteristics of the amplifier section are shown in Figure 11. Amplifier Compensation (Pin 7) The operational amplifier can be compensated for unity gain by a single 300pF capacitor from pin 7 to ground. (See Figure 11.) BASIC PHASE-LOCKED LOOP OPERATION applied to the control terminal of the VCO. If the input frequency, fs, is sufficiently close to fo, the feedback nature of the PLL causes the VCO to synchronize or "lock" with the incoming signal. Once in lock, the VCO frequency is identical to the input signal, except for a finite phase difference. A Linearized Model for PLL When the PLL is in lock, it can be approximated by the linear feedback system shown in Figure 14. Os and Oo are the respective phase angles associated with the input signal and the VCO output, F(s) is the low-pass filter response in frequency domain, and Kd and Ko are the conversion gains associated with the phase comparator and VCO sections of the PLL. DEFINITION OF XR-215A PARAMETERS USED FOR PLL APPLICATIONS DESIGN
Principle of Operation The phase-locked loop (PLL) is a unique and versatile circuit technique which provides frequency selective tuning and filtering without the need for coils or inductors. As shown in Figure 13, the PLL is a feedback system comprised of three basic functional blocks: phase comparator, low-pass filter and voltage-controlled oscillator (VCO). The basic principle of operation of a PLL can be briefly explained as follows: with no input signal applied to the system, the error voltage Vd, is equal to zero. The VCO operates at a set frequency, fo, which is known as the "free-running" frequency. If an input signal is applied to the system, the phase comparator compares the phase and frequency of the input signal with the VCO frequency and generates an error voltage, Ve(t), that is related to the phase and frequency difference between the two signals. This error voltage is then filtered and
VCO Free-Running Frequency, fo The VCO frequency with no input signal is determined by selection of C0 across pins 13 and 14 and can be increased by connecting an external resistor RX between pins 9 and 10. It can be approximated as:
f 0 [ 220 1 ) 0.6 RX C0
where C0 is in mF and RX is in kW. (See Figure 8.)
Input Signal
VS(t) fs
Phase Comparator
Ve(t)
Lowpass Filter
Vd(t)
VO(t) VCO Vd(t)
fo
Figure 13. Block Diagram of a Phase-Locked Loop
Rev. 1.01 16
XR-215A
Lock Range (DwL) The range of frequencies in the vicinity of fo, over which the PLL can maintain lock with an input signal. It is also known as the "tracking" or "holding" range. If saturation or limiting does not occur, the lock range is equal to the loop gain, i.e. DwL = KT = KdKo. Capture Range (DwC) The band of frequencies in the vicinity of fo where the PLL can establish or acquire lock with an input signal. It is also known as the "acquisition" range. It is always smaller than the lock range and is related to the low-pass filter bandwidth. It can be approximated by a parametric equation of the form: DwC DwL |F(jDwC )| where |F(jDwC| is the low-pass filter magnitude response at w = DwC. For a simple lag filter, it can be expressed as: Phase Comparator Gain Kd The output voltage from the phase comparator per radian of phase difference at the phase comparator inputs (pins 4 and 6). The units are volts/radians. (See Figure 9.) VCO Conversion Gain Ko The VCO voltage-to-frequency conversion gain is determined by the choice of timing capacitor C0 and gain control resistor, R0 connected externally across pins 11 and 12. It can be expressed as: Dw C [ Dw L T1
Os -
Kd
F(s)
O0 Ko s
Figure 14. Linearized Model of a PLL as a Negative Feedback System
where T1 is the filter time constant. Amplifier Gain AV The voltage gain of the amplifier section is determined by feedback resistors RF and Rp between pins (8,1) and (2,1) respectively. (See Figure 3 and Figure 4.) It is given by:
K 0 [ 700 (radians/sec/volt) C 0R 0
where C0 is in mF and R0 is in kW. For most applications, recommended values for R0 range from 1kW to 10kW.
AV [
-R F R1 ) RP
where R1 is the (6kW) internal impedance at pin 2.
Rev. 1.01 17
XR-215A
Low-Pass Filter The low-pass filter section is formed by connecting an external capacitor or RC network across terminals 2 and 3. The low-pass filter components can be connected either between pins 2 and 3 or, from each pin to ground. Typical filter configurations and corresponding filter
Lag Filter 2 C1 3 2 R2 C1
transfer functions are shown in Figure 15 where R1 (6kW) is the internal impedance at pins 2 and 3. It should be noted that the rejection of the low pass filter decreases above 2MHz when the capacitor is tied from pin 2 to 3.
Lag Lead Filter 3
t1 = 2R1C1 F(s) = 1 St1
t1 = 2R1C1 t2 = R2C1 F(s) = 1 + St2 1 + S(t1+t2)
2 2 C1 3 C1 C1 R2
3 C1 R2
t1 = R1C1 F(s) = 1 St1
t1 = R1C1 t2= R2C1 1 + St2 F(s) = 1 + S(t1 + t2)
Figure 15.
Note: R1 = 6kW internal resistor.
The natural frequency wn can be calculated from the VCO conversion gain K0, the phase comparator conversion gain Kd, and the low pass filter time constants t1 and t 2 as follows: j+ wn 2 t2 ) 1 K0 * Kd
Then the damping factor j can be calculated using: wn +
K0 * Kd t1 ) t2
Rev. 1.01 18
XR-215A
+12V 5K 5K 0.1mF 0.1mF 2K U1 Cc FM Input 5 6 R0 11 12 10 VEE 9 13 Rx C0 Volume Control
Op Amp
2K
16 VCC 4 XR-215A 15 8 7 300pF 7.5K Demodulated Output 10nF (De-Emphasis) 2K 8K
Phase Comp.
Cc
14
2
31
RF RP 10K C1 C1
Cc Coupling Capacitor 50 50
Figure 16. Circuit Connection for FM Demodulation
APPLICATIONS INFORMATION FM Demodulation Figure 16 shows the external circuit connections to the XR-215A for frequency-selective FM demodulation. The choice of C0 is determined by the FM carrier frequency (see Figure 8.) The low-pass filter capacitor C1 is determined by the selectivity requirements. For carrier frequencies of 1 to 10MHz, C1 is in the range of 10C0 to 30C0. The feedback resistor RF can be used as a "volume-control" adjustment to set the amplitude of the demodulated output. The demodulated output amplitude is proportional to the FM deviation and to resistors R0 and RF for +1% FM deviation it can be approximated as:
V OUT [ R 0R F 1 ) 0.6 mV, rms RX
where all resistors are in kW and RX is the range extension resistor connected across pins 9 and 10. For circuit operation below 5MHz, RX can be omitted. For operation above 5MHz, RX 750W is recommended. Typical output signal/noise ratio and harmonic distortion are shown in Figure 17 and Figure 18 as a function of FM deviation, for the component values shown in Figure 5.
Rev. 1.01 19
XR-215A
Multi-Channel Demodulation The AC digital programming capability of the XR-215A allows a single circuit be time-shared or multiplexed between two information channels, and thereby selectively demodulate two separate carrier frequencies. Figure 19 shows a practical circuit configuration for time-multiplexing the XR-215A between two FM channels, at 1MHz and 1.1MHz respectively. The channel-select logic signal is applied to pin 10, as shown in Figure 19 with both input channels simultaneously present at the PLL input (pin 4). Figure 20 shows the demodulated output as a function of the channel-select pulse where the two inputs have sinusoidal and triangular FM modulation respectively.
80
60
40
0.01%
Figure 17. Output Signal/Noise Ratio as a Function of FM Deviation
0.5%
0 0.01%
Figure 18. Output Distortion as a Function of FM Deviation
Rev. 1.01 20
IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII
1%
Distortion (THD)
IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII
fo =10 MHz fmod = 1 KHz VIN = 20 mV rms (Test Circuit of Figure 5) 0.1% 1.0% 10% 100% Frequency Deviation Df/fo fo =10MHz fmod = 1KHz VIN = 20 mV rms VOUT = Constant @ 2 VPP (Test Circuit of Figure 5) 0.1% 1.0% 10% 100% Frequency Deviation Df/fo
100 Demodulated Output Signal / Noise (dB)
XR-215A
+5V
0.1mF Channel 1 F1=1MHz
1K U1
1K
Channel 2 F2=1.1MHz
0.1mF 6 Phase Comp.
5
16 VCC 4 XR-215A 3K 10K
R0 3K Channel Select 1K 0V Fo=F1 -5V Fo=F2
11 12 10 VEE
10nF -5V
VCO
Op Amp
15 8 7 300pF
Rx 6K
9
13 Co
14 220pF
2
31
7.5K
Demodulated Output 10nF (De-Emphasis)
-5V RP 10K 4nF 4nF
100K
Cc Coupling Capacitor
Figure 19. Time-Multiplexing XR-215A Between Two Simultaneous FM Channels
Rev. 1.01 21
XR-215A
Demodulated Output Channel Select Pulse
Figure 20. Demodulated Output Waveforms for Time-Multiplexed Operation
FSK Demodulation
Figure 21 contains a typical circuit connection for FSK demodulation. When the input frequency is shifted, corresponding to a data bit, the DC voltage at the phase comparator outputs (pins 2 and 3) also reverses polarity. The operational amplifier section is connected as a comparator, and converts the DC level shift to a binary output pulse. One of the phase comparator outputs (pin 3) is AC grounded and serves as the bias reference for the operational amplifier section. Capacitor C1 serves as the PLL loop filter, and C2 and C3 as post-detection filters. Range select resistor, RX, can be used as a fine-tune adjustment to set the VCO frequency.
Typical component values for 300 baud and 1200 baud operation are listed below:
Operating Conditions 300 Baud Low Band: f1 = 1070Hz f2 = 1270Hz High Band: f1 = 2025Hz f2 = 2225Hz 1200 Baud f1 = 1200Hz f2 = 2200Hz Typical Component Values R0 = 5kW, C0 = 0.17mF C1 = C2 = 0.047mF, C3 = 0.033mF R0 = 8kW, C0 = 0.1mF C1 = C2 = C3 = 0.033mF R0 = 2kW, C0 = 0.12mF C1 = C3 = 0.003mF C2 = 0.01mF
Table 1. Typical Component Values for Modems
Note: For 300 Baud operation the circuit can be time-multiplexed between high and low bands by switching the external resistor RX in and out of the circuit with a control signal, as shown in Figure 12.
FSK Generation The digital programming capability of the XR-215A can be used for FSK generation. A typical circuit connection for this application is shown in Figure 22. The VCO frequency can be shifted between the mark (f2) and space (f1) frequencies by applying a logic pulse to pin 10. The circuit can provide two separate FSK outputs: a low level (2.5 Vp-p) output at pin 15 or a high amplitude (10 Vp-p) output at pin 8. The output at each of these terminals is a symmetrical squarewave with a typical second harmonic content of less than 0.3%.
Rev. 1.01 22
XR-215A
+12V 5K 5K 0.1mF 0.1mF 2K 2K 0.1mF FSK Input Ro 11 12 10 VEE 9 13 C0 U1 5 6 Phase Comp. XR-215A 15
Op Amp
16
VCC 4 0.1mF
2K 8K
VCO
8 7 10K
RX 5K
14
2
31
10Vpp VOUT
1mF
10K C1 C2
10K C3
Figure 21. Circuit Connection for FSK Demodulation
Rev. 1.01 23
XR-215A
+12V 5K 5K 0.1mF 0.1mF
U1 5 6 11 12 +5V 0V Keying Input Rx C0 10K F1 0.1mF 3K F2 10 VEE 9 13 VCO
Op Amp
16 VCC 4 XR-215A 15 F1 8 7 10K FSK Output 10VPP 5K F2 FSK Output (Low Level) 2.5VPP
Phase Comp.
14
2
31
Figure 22. Circuit Connection For FSK Generation
Frequency Synthesis In frequency synthesis applications, a programmable counter or divide-by-N circuit is connected between the VCO output (pin 15) and one of the phase detector inputs (pins 4 or 6), as shown in Figure 23. The principle of operation of the circuit can be briefly explained as follows: The counter divides down the oscillator frequency by the programmable divider modulus, N. Thus, when the entire system is phase-locked to an input signal at frequency, fs, the oscillator output at pin 15 is at a frequency (Nfs), where N is the divider modulus. By proper choice of the divider modulus, a large number of discrete frequencies can be synthesized from a given reference frequency. The low-pass filter capacitor C1 is normally chosen to provide a cut-off frequency equal to 0.1% to 2% of the signal frequency, fs.
Rev. 1.01 24
XR-215A
+5V 0.1mF Cc U1 20K 5 6 11 4K 1K 12 10
VEE
Cc Phase Comp. 16 VCC 4 XR-215A 15
Op Amp
Input F=Fs Level Shifter
20K
VCO
VCO Output Fo=NFs Cc 10K
N
Binary Range Select (Optional)
8 7
9 13 Rx C0 -5V
14
2
31 C1
SN7493 or Equivalent
20K C1
Figure 23. Circuit Connection For Frequency Synthesis The circuit was designed to operate with commercially available monolithic programmable counter circuits using TTL logic, such as MC4016, SN5493 or equivalent. The digital or analog tuning characteristics of the VCO can be used to extend the available range of frequencies of the system, for a given setting of the timing capacitor C0. Typical input and output waveforms for N = 16 operation with fs = 100kHz and fo = 1.6MHz are shown in Figure 24.
Figure 24. Typical Input/Output Waveforms for N=16 Top: Input (100kHz) Bottom: VCO Output (1.6MHz)
Rev. 1.01 25
XR-215A
Tracking Filter/Discriminator The wide tracking range of the XR-215A allows the system to track an input signal over a 3:1 frequency range, centered about the VCO free running frequency. The tracking range is maximum when the binary rangeselect (pin 10) is open circuited. The circuit connections for this application are shown in Figure 25. Typical tracking range for a given input signal amplitude is shown in Figure 26. Recommended components are: values of external
1kW < R0 < 4kW and 30 C0 < C1 < 300 C0 where the timing capacitor C0 is determined by the center frequency requirements (see Figure 8.)
+12V 5K 5K 0.1mF 0.1mF 2K U1 5 0.1mF Signal Input Vs Ro 6 Phase Comp. 16 VCC 2K 4 XR-215A 15
Op Amp.
2K
11 12 10 VEE 9 13 C0 VCO
Cc
8 7 300pF
10K
VCO Output
14
2
31
10K Discriminator Output RF
RP 20K C1 C1
50
50
Figure 25. Circuit Connection For Tracking Filter Applications
Rev. 1.01 26
XR-215A
The phase-comparator output voltage is a linear measure of the VCO frequency deviation from its free-running value. The amplifier section, therefore, can be used to provide a filtered and amplified version of the loop error voltage. In this case, the DC output level at pin 15 can be adjusted to be directly proportional to the difference between the VCO free-running frequency, fo, and the input signal, fs. The entire system can operate as a "linear discriminator" or analog "frequency-meter" over a 3:1 change of input frequency. The discriminator gain can be adjusted by proper choice of R0 or RF, for the test circuit of Figure 25, the discriminator output is approximately (0.7 R0RF) mV per % of frequency deviation where R0 and RF are in kW. Output non-linearity is typically less than 1% for frequency deviations up to +15%. Figure 28 shows the normalized output characteristics as a function of input frequency, with R0 = 2kW and RF = 36kW. Crystal-Controlled PLL The XR-215A can be operated as a crystal-controlled phase-locked loop by replacing the timing capacitor with a crystal. A circuit connection for this application is shown in Figure 28. Normally a small tuning capacitor ( 30pF) is required in series with the crystal to set the crystal frequency. For this application the crystal should be operated in its fundamental mode. Typical pull-in range of the circuits is +1kHz at 10MHz. There is some distortion on the demodulated output.
1000
100
10
1.0
0.5
Rev. 1.01 27
IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII
R0 = 2kW Tracking Range 1.0 2.0 Normalized Temperature Range (f/fo)
Signal Input (mV rms)
Figure 26. Tracking Range vs. Input Amplitude (Pin 10 Open Circuited)
XR-215A
Figure 27. Typical Discriminator Output Characteristics for Tracking Filter Applications
+12V 5K 5K 0.1mF 0.1mF 20K U1 5 6 Signal Input Vs 0.01mF 11 12 10 VEE 9 13 1K 30pF 10MHz VCO
Op Amp.
Figure 28. Typical Circuit Connection for Crystal-Controlled PLL.
Rev. 1.01 28
IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII
+3 +2 +1 0 Slope = 50mV Per % Change of Frequency -1 -2 -3 R0 = 2KW RF = 36KW VIN = 50mV rms 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Normalized Tracking Range (f/fo) 16K Phase Comp. 16 VCC 4 XR-215A 15 8 7 300pF 10K 10nF 100K Crystal Fundamental Mode 10nF 50 10K Demodulated Ouput 0.01mF VCO Output 14 2 31 10nF 50
Normalized Output (Volts)
XR-215A
16 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP)
Rev. 1.00
16 1 D
9 8 E1 E A2
Seating Plane
A L A1 B e B1
eA eB
C
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.145 0.015 0.115 0.014 0.030 0.008 0.745 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 0.840 0.325 0.280
MILLIMETERS MIN 3.68 0.38 2.92 0.36 0.76 0.20 18.92 7.62 6.10 MAX 5.33 1.78 4.95 0.56 1.78 0.38 21.34 8.26 7.11
0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.160 15
2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 4.06 15
Note: The control dimension is the inch column
Rev. 1.01 29
XR-215A
16 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC)
Rev. 1.00
D
16
9
E
1 8
H
C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.398 0.291 MAX 0.104 0.012 0.020 0.013 0.413 0.299
MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 MAX 2.65 0.30 0.51 0.32 10.50 7.60
0.050 BSC 0.394 0.016 0 0.419 0.050 8
1.27 BSC 10.00 0.40 0 10.65 1.27 8
Note: The control dimension is the millimeter column
Rev. 1.01 30
XR-215A Notes
Rev. 1.01 31
XR-215A
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1975 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.01 32

▲Up To Search▲

Price & Availability of XR-215ACP

	To Download XR-215ACP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .